The present invention relates to a semiconductor device and a technique of manufacturing it, and more particularly to a technique that can be effectively applied to a semiconductor device on whose wiring board a semiconductor chip is mounted.
For instance, there is a technique to increase the freedom of electrode arrangement on the main surface of the semiconductor device by arranging a plurality of electrodes (pads) in a zigzag pattern on the main surface of a semiconductor device and providing power supply electrodes and grounding electrodes extending along the sides constituting the main surface and arranged in a frame shape surrounding the central part of the semiconductor device. This makes it possible to cope with an increase in the number of electrodes (use of multiple pins) along with the functional sophistication of semiconductor devices and a reduction in semiconductor device size (see Patent Reference 1 for instance)
Patent Reference 1: Japanese Unexamined Patent Publication No. 2001-244293